Gate-First/Channel-Last Process for High-Performance a-IGZO Gate-All-Around Nanosheet FETs

This work demonstrated a high-performance gate-all-around (GAA) a-IGZO nanosheet transistor fabricated using a simplified gate-first, channel-last process. The key functional layers (gate insulator, channel) are deposited continuously in one low-temperature atomic layer deposition (ALD) step, avoiding plasma-induced damage to the IGZO channel. The fabricated nanoscale transistors exhibit excellent electrical characteristics, including a sharp subthreshold swing (SS = 68.9 mV/dec), a high drive current (I ${}_{\mathbf {\textit {on}}} = 165~\mu $ A/ $\mu $ m), a near-zero threshold voltage (V ${}_{\mathbf {\textit {th}}} =$ -84 mV), and small drain-induced barrier lowering (DIBL = 13 mV/V). Besides, high device stability is achieved with $\Delta $ V ${}_{\mathbf {\textit {th}}}$ of −26 mV in negative bias temperature instability (NBTI) test and + 28 mV in positive bias temperature instability (PBTI) test for 3600s at $85~^{\circ }$ C. The process is fully compatible with back-end-of-line (BEOL) integration and is promising for scalable monolithic 3D integration.