采用高功函数氮化钼金属栅垂直无结柱状存取晶体管的创新DRAM单元

In this work, we demonstrate an innovative dynamic random access memory (DRAM) cell design featuring a vertical junctionless pillar access transistor with a high work-function (WF) molybdenum nitride (MoN) metal gate, enabling enhanced performance and efficiency. By depositing MoN over the gate dielectric at temperatures below $600~^{\circ}$ C, we achieved a wrapped-gate transistor array with significantly improved electrical characteristics. Compared to conventional titanium nitride (TiN) gates, the MoN gate exhibits a 0.22-V positive shift in flat-band voltage (VFB) to −0.38 V and a 35% increase in threshold voltage ( ${V}_{\text {th}}\text {)}$ to 0.35 V while maintaining identical on-state current (7.6 $\boldsymbol {\mu }$ A/cell) and subthreshold swing (SS) (82.3 mV/dec). These advancements address critical challenges in DRAM scaling, including leakage reduction and noise immunity, without compromising device performance. The MoN gate’s superior WF ( $\boldsymbol {\Phi }_{\text {m}}\text {)}$ enables enhanced depletion in the n-type doped channel, ensuring stable operation at 3.3 V with a projected lifetime exceeding ten years. This study establishes MoN as a promising gate material for high-performance vertical junctionless pillar transistors, offering a scalable solution for next-generation 1T1C DRAM architectures.