28纳米1T1R阻变存储器阵列中存取晶体管引发的可靠性退化优化与抑制

Recent investigations of one-transistor-one-resistive random access memory (RRAM) (1T1R) memory arrays at 40 and 28 nm technology nodes indicate that access transistor reliability represents a critical limiting factor for array endurance in scaled technology nodes, particularly due to overdrive stress-induced degradation effects. This work presents a comprehensive solution for enhancing access transistor reliability in 1T1R RRAM arrays at advanced technology nodes. By engineering the gate oxide and channel profile of the access transistors, significant improvements in array endurance are demonstrated at the 28 nm node. Furthermore, a voltage optimization scheme is developed to mitigate degradation in half-selected devices, enabling further endurance enhancement. This work offers new insights and practical design guidelines for developing high-reliability 1T1R memory arrays in advanced technology nodes.