基于解析模型的标准单元互补场效应晶体管寄生电容提取策略

Complementary FET (CFET) technology is attracting widespread interest as one of the most promising scaling boosters. The additional interconnect layer required for the bottom device in CFET results in a more complex distribution of parasitic capacitance. In this article, we propose a strategy to extract the parasitic capacitance of CFET in standard cell (SDC). Considering the unique multilayer structure of CFET and the practical requirements for circuit design, the interconnections between gates can be categorized into five distinct configurations. Each configuration is further divided into three styles. The capacitance associated with the fixed-style part remains unchanged regardless of design variations and should be included in the compact model of the transistor. Each style is modeled using analytical approaches. For the first time, we evaluate the parasitic capacitance between the interconnections of PFET and NFET in CFET. The comparison between the model and numerical field solver simulation results, along with the transient simulation results obtained by applying the proposed strategy to circuits, comprehensively validates both the feasibility of the strategy and the accuracy of the model.