面向三相四线制电压源逆变器的降采样重复控制设计方法

The three-phase, four-leg voltage source inverter (3P4L-VSI) is an effective transformer-less topology in four-wire stand-alone applications, mainly when dealing with nonlinear and unbalanced loads. Repetitive controllers (RCs) are known to achieve a reduced total harmonic distortion (THD) when supplying nonlinear loads. However, they introduce a high number of poles in the unit circle of the z-plane, which affects stability and requires a large amount of stored previous sampled data. The number of poles and memory requirements can be reduced by a factor of $m$ when RCs are sampled $m$ times lower than the sampling frequency. Integer and fractional phase-lead (PL) compensation can be used for these controllers to stabilize the closed-loop system. While fractional phase lead enhances phase compensation accuracy, it complicates the design and implementation of the control law. This article proposes an approach to design multirate control systems with downsampled RC for the 3P4L-VSI, ensuring stability by strategically placing the closed-loop poles through state-feedback. The proposal enables the use of an integer PL compensator, which is proposed to be designed in this article through a closed-form procedure. In addition, it eliminates the necessity for a low-pass filter (LPF) in the internal model, allowing the rejection of periodic disturbances, including all odd harmonics up to the downsampled Nyquist frequency, which enables a low-voltage THD under nonlinear loads. Using the proposed design, the RC is downsampled by a factor of $m =8$ for the $\alpha $ - and $\beta $ -axes, and $m =10$ for the zero-axis, following a closed-form design procedure. The proposal is validated on a 5-kW inverter prototype, achieving a voltage THD below 0.46% under nonlinear load and ensuring a transient voltage settling time within 80 ms for a step load variation.