并联运行的数字电流模式控制串联电容降压变换器稳定性分析与控制器设计

The design of high-performance, stable digital current-mode control (DCMC) for series capacitor buck (SCB) converters presents significant challenges due to structural changes in series capacitor dynamics and inherent sampling delays. The design based on continuous-time (CT) small-signal models is not sufficient to fully explore the performance and stability. In this article, a novel DCMC strategy is proposed, which employs one sample per cycle and retains the stability of the SCB converter. Possible evolutions of the inductor current are identified between the two sampling points. A generic discrete-time (DT) modeling framework is developed, which accurately captures large-signal behavior. The DT model enables detailed analysis of nonlinear effects, particularly those arising from high controller gains and sampling delays. A DT small-signal model is derived for the nominal case, with both small- and large-signal models validated through SIMPLIS simulations. The proposed DT model successfully predicts instabilities that CT counterparts fail to capture and provides a robust framework for designing stable cycle-by-cycle control and achieving fast dynamic response. The method is validated with a 12–1-V, 60-W, 1-MHz hardware prototype implemented on an FPGA. The stability boundary is further improved, and a comparative study with prior work is presented. In addition, the scalability of the design is demonstrated by interleaving two SCB converters, highlighting the effectiveness of the proposed approach.