具有增强dVSW/dt抗噪能力、负VSW耐受性及开通dVSW/dt可控性的单片GaN功率集成电路

This study presents methods to enhance the reliability of monolithic gallium nitride (GaN) half-bridge power integrated circuits (ICs) under transient electrical stress during high-speed switching. An on-chip ground separation design isolates ground bounce caused by rapid current changes, preventing input breakdown and false triggering in both half-bridge channels. A robust level shifter is developed to enable signal translation between separated grounds, using a dual common-gate differential pair structure to block the propagation of d $V_{\mathrm {SW}}$ /dt noise to downstream circuits, while maintaining low propagation delay. This design simultaneously extends the operational range of the level shifter to a sufficiently low negative $V_{\mathrm {SW}}$ . Furthermore, a gate driver with externally adjustable drive strength mitigates ringing and overshoot without introducing parasitic elements into the gate loop, preserving GaN gate reliability. Fabricated in a 1- $\mu $ m GaN-on-silicon process, a 100 V monolithic GaN power IC incorporating these techniques demonstrates immunity to 130 V/ns d $V_{\mathrm {SW}}$ /dt and a sub-10.4 ns delay, validated experimentally. The chip’s tolerance to −15 V negative voltage and its output strength adjustability are also experimentally confirmed.